1. Technical Field
The present invention generally relates to an integrated circuit and in particular to an integrated circuit with stacked computational units and configurable through vias.
2. Description of the Related Art
Traditionally, designers of integrated circuits (chips) with multiple computational units have distributed the computational units in a same horizontal plane of a chip and have connected the computational units to each other using buses. However, as the number of computational units in conventional chip designs has increased, a footprint of an associated chip and a bus length of buses that connect the computational units to each other has also increased. In general, increasing a footprint of a chip increases a cost of the chip. Moreover, increasing bus lengths in a chip increases bus transmission delays, which may limit system performance.
In an attempt to address the footprint and transmission delay issues associated with conventional chips, chip designers have designed three-dimensional (3D) chips in which two or more layers of active electronic components are integrated vertically and horizontally in a single chip. According to a conventional die-on-die manufacturing technology that has been employed to build 3D chips, electronic components are built on multiple die that are aligned and bonded to form a 3D chip. At least some 3D chips have employed through silicon vias (TSVs) that pass through a die between active layers and/or between an active layer and an external bond pad. According to the conventional die-on-die manufacturing technology, TSV creation can be performed before or after dies are bonded. However, when a via included in a bus (i.e., a set of vias) of a chip manufactured according to the conventional die-on-die manufacturing technology is open, the chip is usually scrap.